1. Field of the Invention
The invention is related to Current Mode Logic (CML) and Emitter Coupled Logic (ECL) circuits.
2. Related Art
Current mode logic (CML) circuits have many applications including multiplexing, frequency division, and implementing logical functions such as AND, NAND, OR, and XOR. FIG. 1 is a block diagram depicting a prior art CML circuit 100. The CML circuit 100 comprises a buffer/inverter module 102, an emitter follower module 104 and a two-level CML gate 106. The buffer/inverter module 102 is used to drive the transistors Q9 and Q10 of the two-level CML gate 106. The buffer/inverter module 102 may be replaced with another module (e.g., a two-level CML gate) that is suitable for driving the transistors Q9 and Q10. The emitter follower module 104 is used to ensure that the buffer/inverter module 102 is compatible with the direct current (DC) level required for the base terminals B9 and B10 of the transistors Q9 and Q10, respectively.
The buffer/inverter module 102 comprises transistors Q1 and Q2 and resistors R1 and R2. The transistor Q1 has a base terminal B1, a collector terminal C1 and an emitter terminal E1. The transistor Q2 has a base terminal B2, a collector terminal C2 and an emitter terminal E2. The resistor R1 is coupled between the voltage source Vs and the collector terminal C1. The resistor R2 is coupled between the voltage source Vs and the collector terminal C2. The emitter terminal E1 and the emitter terminal E2 are coupled to each other and to a current source 110.
The emitter follower module 104 comprises transistors Q3 and Q4. The transistor Q3 has a base terminal B3, a collector terminal C3 and an emitter terminal E3. The base terminal B3 is coupled to a node 124 between the resistor R2 and the collector terminal C2. The emitter terminal E3 is coupled to a current source 112. The transistor Q4 has a base terminal B4, a collector terminal C4 and an emitter terminal E4. The base terminal B4 is coupled to a node 122 between the resistor R1 and the collector terminal C1. The emitter terminal E4 is coupled to a current source 114. The collector terminals C3 and C4 are coupled to the voltage source Vs.
The two-level CML gate 106 comprises transistors Q5, Q6, Q7, Q8, Q9, and Q10 as well as the resistors R5, R6, R7, R8. The transistor Q5 has a base terminal B5, a collector terminal C5, and an emitter terminal E5. A resistor R5 couples between collector terminal C5 and the voltage source Vs. The transistor Q6 has a base terminal B6, a collector terminal C6, and an emitter terminal E6. A resistor R6 couples between collector terminal C6 and the voltage source Vs. The emitter terminals E5 and E6 are coupled to each other.
The transistor Q7 has a base terminal B7, a collector terminal C7, and an emitter terminal E7. A resistor R7 couples between collector terminal C7 and the voltage source Vs. The transistor Q8 has a base terminal B8, a collector terminal C8, and an emitter terminal E8. A resistor R8 couples between collector terminal C8 and the voltage source Vs. The emitter terminals E7 and E8 are coupled to each other.
The transistor Q9 has a base terminal B9, a collector terminal C9, and an emitter terminal E9. The base terminal B9 is coupled to a node 128 between the emitter terminal E4 and the current source 114. The emitter terminal E9 is coupled to a current source 116. The collector terminal C9 is coupled to a node 130 between the emitter terminal E5 and the emitter terminal E6.
The transistor Q10 has a base terminal B10, a collector terminal C10, and an emitter terminal E10. The base terminal B10 is coupled to a node 126 between the emitter terminal E3 and the current source 112. The emitter terminal E10 is coupled to a current source 116. The collector terminal C10 is coupled to a node 132 between the emitter terminal E7 and the emitter terminal E8.
When the CML circuit 100 is in operation, the base terminals B1 and B2 receive inputs for driving the two-level CML gate 106. The two-level CML gate 106 may receive inputs via base terminal B5, B6, B7, and B8, and may provide output via nodes 151-154. The minimum voltage supply required to operate the CML circuit 100 is equal to the sum of the voltage drops across the resistor R1, the base-emitter connection for the transistor Q4, the base-emitter connection for the transistor Q9, and the current source 116. This minimum supply voltage requirement is typically around 2.1 Volts for a circuit temperature of 30xc2x0 C. and around 2.3 Volts for a circuit temperature ofxe2x88x9230xc2x0 C.
Current Mode Logic circuits such as, for example, CML circuit 100, are frequently used in portable wireless devices where there is a continuing need for lower voltage supply requirements (e.g., 1.8 Volts or less). The need for lower voltage supply requirements is especially great for small wireless devices that run at high frequencies (e.g., over 1 GHz). Therefore, it is desirable to address these and/or other needs related to CML circuits.
The invention provides a low voltage CML circuit. In one embodiment of the invention, a current mode logic (CML) circuit includes an emitter follower circuit, a CML gate, and a Schottky diode that is coupled between the emitter follower circuit and the CML gate.